[DRC REQP-1712] Input clock driver: Unsupported PLLE2_ADV connectivity. The signal u_clk_wiz_0/inst/clk_in1 on the u_clk_wiz_0/inst/plle2_adv_inst/CLKIN1 pin of u_clk_wiz_0/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.
According to the prompt information, there should be a problem with the configuration of the clocking wizard.
After selecting PLL, adjust the source from “single ended clock capable pin” to “global buffer”. No error will be reported when implementing again.
- MYSQL Error: Out of sort memory, consider increasing server sort buffer size; nested exception is java.sql.SQLException: Out of sort memory, consider increasing server sort buffer size
- Type switch in golang
- How to Solve Mysql Error 1206: The total number of locks exceeds the lock table size
- Oracle: db_22.214.171.124.0_Linux-x86-64: dbca Customized mode:ORA-07202: sltln: invalid parameter to sltln.
- [Solved] QT project Compile error: ‘:: clock_t’ has not been declared using ::clock_t;
- [Solved] MySQL Error: ERROR 1615 (HY000): Prepared statement needs to be re-prepared
- How to Solve MYSQL Error: mysqldump: Error 2013
- Streams AQ: enqueue blocked on low memory wait event causes slow expdp export
- Ubuntu failed to install libssl dev (depending on aptitude to manage degraded software) and recorded the list of installed software in dpkg
- The usage of WebKit text size adjust