Today, when we do a simple MCU read-write experiment of Bram in FPGA, the experiment is very successful at low frequency. When we increase the frequency from low frequency to 552.96mhz through PLL, we find that vivado prompts the following information:

Run “report”_ “Timing” or “report”_ timing_ After the “summary” command, you will notice WNS, TNS, WHS, and ths.

WNS stands for worst negative slack

TNS represents the total negative slack, that is, the sum of the paths of negative timing margin.

Whs stands for worst hold slack

Th represents the total hold slack, that is, the sum of the paths with negative hold slack.

These values tell the designer the difference between the design and timing requirements. If it is a positive value, it means that the timing requirements can be met; if it is a negative value, it means that the timing requirements cannot be met.

But it doesn’t mean that the time sequence warning function can’t be realized, it’s just that the project is unstable. There will be problems if you add or delete modules or even recompile them. At this time, you can open implementation to see the location of the timing warning.

The so-called timing can not meet the requirements means that it can not meet the establishment and maintenance time, so we should pay attention to the timing constraints.

I ignored these warning messages and continued to download them to the board. As a result, the experiment was successful.

I guess: if the logic code of FPGA is enlarged, there will be a problem.

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